Three dimensional structure memory

CAFC
  • US 8,933,570 B2
  • Filed: 03/17/2009
  • Issued: 01/13/2015
  • Est. Priority Date: 04/04/1997
  • Status: Expired due to Term
First Claim
Patent Images

1. An apparatus comprising:

  • a first integrated circuit having a thickness Th1;

    a second integrated circuit in a stacked relationship with and adjacent to the first integrated circuit having a thickness Th2; and

    hundreds of vertical interconnect segments interconnecting the first and second integrated circuits including a plurality of vertical interconnect segments having lengths of Th1+Th2 or less, wherein the plurality of vertical interconnect segments form interconnections only between a pair of adjacent integrated circuits;

    wherein at least one of the first integrated circuit and the second integrated circuit is thin and substantially flexible and comprises a thinned, substantially flexible monocrystalline semiconductor substrate of one piece made from a semiconductor wafer thinned from a backside thereof by at least one of abrasion, etching and parting, and subsequently polished or smoothed to form a polished or smoothed surface.

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