Three dimensional structure memory

• US 8,933,570 B2
• Filed: 03/17/2009
• Issued: 01/13/2015
• Est. Priority Date: 04/04/1997
• Status: Expired due to Term

• Current Assignee: Elm 3DS Innovations LLC
• Original Assignee: ELM TECHNOLOGY CORPORATION
• Inventors: Leedy, Glenn J.
• Primary Examiner(s): GREEN, TELLY D
• Application Number:
  US12/405,239
• Publication Number:
  US 20090219772A1
• Time in Patent Office: 2,128 Days
• Field of Search: 257/777, 257/778, 257/685, 257/686, 365/200, 365/201, 365/230.6
• US Class Current: 257/777
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/8083 Solid-solid interdiffusion
• CPC Class Codes: H01L 2224/8384 Sintering
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/02 Semiconductor bodies ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Claims

1. An apparatus comprising:

a first integrated circuit having a thickness Th₁;

a second integrated circuit in a stacked relationship with and adjacent to the first integrated circuit having a thickness Th₂; and

hundreds of vertical interconnect segments interconnecting the first and second integrated circuits including a plurality of vertical interconnect segments having lengths of Th₁+Th₂ or less, wherein the plurality of vertical interconnect segments form interconnections only between a pair of adjacent integrated circuits;

wherein at least one of the first integrated circuit and the second integrated circuit is thin and substantially flexible and comprises a thinned, substantially flexible monocrystalline semiconductor substrate of one piece made from a semiconductor wafer thinned from a backside thereof by at least one of abrasion, etching and parting, and subsequently polished or smoothed to form a polished or smoothed surface.

2. The apparatus of claim 1, further comprising at least one memory integrated circuit and at least one logic integrated circuit, wherein the at least one logic integrated circuit performs testing of the at least one memory integrated circuit.

3. The apparatus of claim 1, further comprising at least one memory integrated circuit having multiple memory locations including at least one memory location used for sparing, wherein data from the at least one memory location on the at least one memory integrated circuit is used instead of data from a defective memory location on the at least one memory integrated circuit.

4. The apparatus of claim 1, further comprising at least one memory integrated circuit and at least one logic integrated circuit, wherein the at least one logic integrated circuit performs programmable gate line address assignment with respect to the at least one memory integrated circuit.

5. The apparatus of claim 1, wherein the at least one of the first integrated circuit and the second integrated circuit is formed with a low stress dielectric material, wherein the low stress dielectric material is at least one of a silicon dioxide dielectric material and an oxide of silicon dielectric material and has a tensile stress of less than 5×

10⁸ dynes/cm².

6. The apparatus of claim 5, wherein the plurality of vertical interconnect segments pass through the thinned, substantially flexible monocrystalline semiconductor substrate and are insulated therefrom by a low-stress silicon-based dielectric material with a tensile stress of less than 5×

10⁸ dynes/cm².

7. The apparatus of claim 5, wherein each of the plurality of vertical interconnect segments comprises a conductive land formed on a surface of the first integrated circuit and a conductive land formed on a surface of the second integrated circuit and passes through the thinned, substantially flexible monocrystalline semiconductor substrate and is insulated therefrom by a low-stress silicon-based dielectric material with a tensile stress of less than 5×

10⁸ dynes/cm².

8. The apparatus of claim 5, wherein each of the plurality of vertical interconnect segments comprises a conductive land formed on a surface of the first integrated circuit, a conductive land formed on a surface of the second integrated circuit, and a via formed within one of the first and second integrated circuits and passes through the thinned, substantially flexible monocrystalline semiconductor substrate and is insulated therefrom by a low-stress silicon-based dielectric material with a tensile stress of less than 5×

10⁸ dynes/cm².

9. The apparatus of claim 8, wherein the conductive land formed on the surface of the first integrated circuit and the conductive land formed on the surface of the second integrated circuit are bonded together.

10. The apparatus of claim 8, wherein the conductive land formed on the surface of the first integrated circuit and the conductive land formed on the surface of the second integrated circuit are bonded together by thermal diffusion bonding.

11. The apparatus of claim 5, wherein the plurality of vertical interconnect segments are grouped to form a dense interconnect array and pass through the thinned, substantially flexible monocrystalline semiconductor substrate and are insulated therefrom by a low-stress silicon-based dielectric material with a tensile stress of less than 5×

10⁸ dynes/cm².

12. The apparatus of claim 5, wherein the first integrated circuit and the second integrated circuit are formed with one of single crystal semiconductor material and polycrystalline semiconductor material.

13. The apparatus of claim 5, wherein one of the first and second integrated circuits are formed using a different process technology than another of the first and second integrated circuits, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.

14. The apparatus of claim 5, wherein at least one of the first and second integrated circuits comprises a microprocessor.

15. The apparatus of claim 5, wherein the plurality of vertical interconnect segments pass through holes formed in the thinned, substantially flexible monocrystalline semiconductor substrate and are insulated therefrom by a low-stress silicon-based dielectric material with a tensile stress of less than 5×

10⁸ dynes/cm².

16. The apparatus of claim 5, wherein the plurality of vertical interconnect segments form continuous vertical interconnections that connect circuitry of the first and second integrated circuits, and wherein the plurality of vertical interconnect segments pass through the thinned, substantially flexible monocrystalline semiconductor substrate and are insulated therefrom by a low-stress silicon-based dielectric material with a tensile stress of less than 5×

10⁸ dynes/cm².

17. The apparatus of claim 5, wherein information processing is performed on data routed between circuitry on the first and second integrated circuits.

18. The apparatus of claim 5, wherein at least one of the integrated circuits has reconfiguration circuitry.

19. The apparatus of claim 5, including at least one logic integrated circuit having logic for performing at least one of the following functions:

virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.

20. The apparatus of claim 5, further comprising:

a memory array having a plurality of memory cells, a plurality of data lines, and a plurality of gate lines, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to a gate control signal on one of said gate lines;

circuitry for generating a gate control signal in response to an address, including means for mapping addresses to gate lines; and

a controller for determining that one of said memory cells is defective and for altering said mapping to eliminate references to said one of said memory cells.

21. The apparatus of claim 5, further comprising:

one or more controller integrated circuits;

one or more memory integrated circuits;

a plurality of data lines and a plurality of gate lines on each memory integrated circuit;

an array of memory cells on each memory integrated circuit, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines;

a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines, said address assignments for determining which of said gate lines is selected for each programmed address assignment; and

controller logic for determining that one of said memory cells is defective and for altering, in at least one instance, said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines.

22. The apparatus of claim 21, wherein said controller logic tests said memory cells periodically to determine if any of said memory cells is defective and wherein said controller logic eliminates references in said address assignments to gate lines that cause detected defective memory cells to couple data values to said data lines.

23. The apparatus of claim 21, further comprising programmable logic to prevent the use of data values from data lines when gate lines cause detected defective memory cells to couple data values to said data lines.

24. The apparatus of claim 21, wherein said memory cells are arranged within physical space in a physical order and are arranged within an address space in a logical order, wherein said physical order of at least one memory cell is different than the logical order of that memory cell.

25. The apparatus of claim 21, wherein external testing of the controller logic together with testing by the controller logic of the memory cells achieves a functional testing of a preponderance of the memory cells.

26. The apparatus of claim 21, wherein testing by the controller logic of the memory cells substantially reduces or eliminates the need for external testing of the memory cells of the one or more memory integrated circuits.

27. The apparatus of claim 21, wherein altering said address assignments comprises preventing the use of at least one defective gate line and replacing references to memory cells addressed using said defective gate line with references to spare memory cells addressed using a spare gate line.

28. The apparatus of claim 5, wherein the first integrated circuit is fabricated using one process technology, and the second integrated circuit is fabricated using a different process technology.

29. The apparatus of claim 5, wherein at least one of the integrated circuits has a thickness of 50 microns or less.

30. The apparatus of claim 5, wherein at least one of the first integrated circuit and the second integrated circuit comprises a monocrystalline semiconductor substrate.

31. The apparatus of claim 5, wherein at least one of said vertical interconnect segments comprises a conductive center portion and a dielectric portion surrounding the center portion, the dielectric portion having tensile stress of less than 5×

10⁸ dynes/cm².

32. The apparatus of claim 5, wherein at least two of the following:

at least one of the plurality of vertical interconnect segments extends through at least one of said integrated circuits and comprises a conductive center portion and a surrounding insulating portion having tensile stress of less than 5×

10⁸ dynes/cm²;

the plurality of vertical interconnect segments are each formed of a first metal contact on the first integrated circuit and a second aligned metal contact on the second integrated circuit bonded together;

the vertical interconnect segments are formed at the time of bonding between the adjacent integrated circuits to interconnect the adjacent integrated circuits;

at least one of the integrated circuits comprises a substrate that is one of a thinned monocrystalline semiconductor substrate and a thinned polycrystalline semiconductor substrate;

at least one of the integrated circuits is formed using a different process technology than another one of the integrated circuits, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance;

at least one of the integrated circuits comprises a microprocessor;

information processing is performed on data routed between the integrated;

at least one of the integrated circuits has reconfiguration circuitry;

at least one of the integrated circuits has logic circuitry formed thereon for performing at least one function from the group consisting of;

virtual memory management, error correcting codes. (ECC), indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.

33. The apparatus of claim 1, further comprising a low-stress silicon-based dielectric layer formed above the thinned, substantially flexible monocrystalline semiconductor substrate and having a tensile stress of less than 5×

10⁸ dynes/cm², wherein;

the polished or smoothed surface of the thinned, substantially flexible monocrystalline semiconductor substrate is polished or smoothed to reduce vulnerability to fracture as a result of flexing; and

the at least one of the first integrated circuit and the second integrated circuit has edges that define its size in area; and

the thinned, substantially flexible monocrystalline semiconductor substrate extends in one piece across a substantial portion of the area between the edges.

34. The apparatus of claim 1, further comprising a low-stress silicon-based dielectric layer formed above the thinned, substantially flexible monocrystalline semiconductor substrate and having a stress of less than 5×

10⁸ dynes/cm² tensile, wherein;

the polished or smoothed surface of the thinned, substantially flexible monocrystalline semiconductor substrate is polished or smoothed to reduce vulnerability to fracture as a result of flexing; and

the at least one of the first integrated circuit and the second integrated circuit comprises a singulated die having a die area defined by its perimeter; and

the thinned, substantially flexible monocrystalline semiconductor substrate extends in one piece across a substantial portion of the die area.

35. The apparatus of claim 1, further comprising a low-stress silicon-based dielectric layer formed above the thinned, substantially flexible monocrystalline semiconductor substrate and having a stress of less than 5×

10⁸ dynes/cm² tensile, wherein;

the polished or smoothed surface of the thinned, substantially flexible monocrystalline semiconductor substrate is polished or smoothed to reduce vulnerability to fracture as a result of flexing; and

the at least one of the first integrated circuit and the second integrated circuit is substantially flexible based on the thinned, substantially flexible monocrystalline semiconductor substrate being substantially flexible and the stress of the low stress silicon-based dielectric layer being less than 5×

10⁸ dynes/cm² tensile.

36. The apparatus of claim 1, further comprising a low-stress silicon-based dielectric layer formed above the thinned, substantially flexible monocrystalline semiconductor substrate and having a tensile stress of less than 5×

10⁸ dynes/cm²; and

,

wherein the thinned, substantially flexible monocrystalline semiconductor substrate comprises a plurality of etched through-holes each surrounding a conductor and an insulator of one of the plurality of vertical interconnect segments, the insulator comprising low-stress silicon-based dielectric material having a tensile stress of less than 5×

10⁸ dynes/cm² surrounding the conductor and isolating the conductor from the thinned, substantially flexible monocrystalline semiconductor substrate; and

the polished or smoothed surface of the thinned, substantially flexible monocrystalline semiconductor substrate is polished or smoothed to reduce vulnerability to fracture as a result of flexing.

37. The apparatus of claim 5, further comprising a plurality of other integrated circuits;

and,

wherein;

the first integrated circuit and the second integrated circuit and the plurality of other integrated circuits are in stacked relationship and form a stacked integrated circuit memory structure;

at least a majority of the stacked integrated circuit memory structure is partitioned into a plurality of block stacks, each block stack comprising at least one memory array controller block from at least one of the first integrated circuit and second integrated circuit, a plurality of memory array blocks from the plurality of other integrated circuits and an array of vertical interconnects that vertically interconnect the at least one memory array controller block and the plurality of memory array blocks and pass through at least one of the at least one memory array controller block and the plurality of memory array blocks, wherein the at least one memory array controller block comprises circuitry that performs memory accesses with the plurality of memory array blocks; and

,

at least two of the plurality of block stacks can independently and simultaneously perform memory accesses within the stacked integrated circuit memory structure, wherein the array of vertical interconnects of the at least two of the plurality of block stacks can independently and simultaneously transfer data during said memory accesses.

38. The apparatus of claim 37, wherein at least one block stack of the plurality of the block stacks comprises at least one memory array controller block comprising ECC circuitry that performs error correction on read data from at least one of the memory array blocks of said at least one block stack, wherein the read data is transferred through one or more of the array of vertical interconnects of said at least one block stack.

39. The apparatus of claim 38, wherein the read data includes ECC data used by the ECC circuitry to perform error correction on the read data.

40. The apparatus of claim 37, wherein at least one block stack of the plurality of the block stacks comprises at least one memory array controller block comprising reconfiguration circuitry that performs reconfiguration of the array of vertical interconnects of the at least one block stack to avoid using one or more defective memory portions of the plurality of memory array blocks of the at least one block stack.

41. The apparatus of claim 40, wherein the reconfiguration circuitry substitutes for the one or more defective memory portions of the plurality of memory array blocks one or more redundant memory portions from at least one of the plurality of memory array blocks.

42. The apparatus of claim 41, wherein the one or more defective memory portions comprise defective gate lines of the plurality of memory array blocks and the one or more redundant memory portions comprise redundant gate lines of the plurality of memory array blocks.

43. The apparatus of claim 37, wherein at least one block stack of the plurality of block stacks comprises at least one memory array controller block further comprising reconfiguration circuitry that performs reconfiguration of the array of vertical interconnects of the at least one block stack to avoid using one or more defective vertical interconnects of the at least one block stack.

44. The apparatus of claim 37, wherein at least one block stack of the plurality of block stacks comprises at least one memory array controller block further comprising refresh circuitry that performs refresh of one or more memory portions of the plurality of memory array blocks of the at least one block stack, wherein the refresh circuitry performs refresh of the one or more memory portions using one or more of the vertical interconnects of said at least one block stack.

45. The apparatus of claim 37, wherein at least one block stack of the plurality of block stacks comprises at least one memory array block controller further comprising test circuitry that performs testing of one or more memory portions of the plurality of memory array blocks of the at least one block stack, wherein the test circuitry tests the one or more memory portions using one or more of the vertical interconnects of said at least one block stack.

46. The apparatus of claim 1, wherein:

the first integrated circuit is a memory controller circuit layer; and

, the second integrated circuit is a first memory circuit layer comprising at least one silicon-based low stress dielectric layer and at least one conductive layer, wherein the at least one low-stress silicon-based dielectric layer has a stress of less than 5×

10⁸ dynes/cm² tensile; and

further comprising;

at least one low-stress silicon-based dielectric layer formed in the at least one of the first integrated circuit and the second integrated circuit and above the thinned, substantially flexible monocrystalline semiconductor substrate, wherein the low-stress silicon-based dielectric layer has a stress of less than 5×

10⁸ dynes/cm² tensile; and

a plurality of memory circuit layers each memory circuit layer comprising at least one silicon-based low stress dielectric layer and at least one conductive layer, wherein the at least one low-stress silicon-based dielectric layer has a stress of less than 5×

10⁸ dynes/cm² tensile.

47. The apparatus of claim 46, wherein the polished or smoothed backside enables the thinned, substantially flexible monocrystalline semiconductor substrate to be substantially flexible, and the polished or smoothed backside reduces vulnerability of the thinned, substantially flexible monocrystalline semiconductor substrate to fracture as a result of flexing.

48. The apparatus of claim 46, wherein the apparatus is flexible through a combination of the thinned, substantially flexible monocrystalline semiconductor substrate having the polished or smoothed backside, low stress of the at least one low stress silicon-based dielectric layer formed above the thinned, substantially flexible monocrystalline semiconductor substrate, and low stress stress of the at least one silicon-based low stress dielectric layer of each of the first memory circuit layer and the plurality of memory circuit layers.

49. The apparatus of claim 46, further comprising a plurality of interconnect conductors extending vertically through at least one of the plurality of memory circuit layers;

and, low stress dielectric insulators insulating the interconnect conductors from the at least one conductive layer, wherein the low-stress dielectric insulators comprise silicon-based dielectric material with a stress of less than 5×

10⁸ dynes/cm² tensile.

50. The apparatus of claim 49, wherein the plurality of interconnect conductors comprise polysilicon.

51. The apparatus of claim 46, wherein at least one of:

the memory controller circuit layer, the first memory circuit layer, and the plurality of memory circuit layers together form a memory, the memory being reconfigurable by operation of the memory controller circuit layer;

the memory controller circuit layer further comprising circuitry for performing functional testing of one or more memory portions of the first memory circuit layer and the plurality of memory circuit layers, wherein the test circuitry performs tests of the one or more memory portions of the first memory circuit and the plurality of memory circuit layers using one or more of the interconnect conductors;

a process technology used to make the memory controller circuit layer is different from a process technology used to make the first memory circuit layer and the plurality of memory circuit layers.

52. The apparatus of claim 51, wherein the apparatus is flexible through a combination of the thinned, substantially flexible monocrystalline semiconductor substrate having the polished or smoothed backside, low stress of the at least one low stress silicon-based dielectric layer formed above the thinned, substantially flexible monocrystalline semiconductor substrate, and low stress of the at least one silicon-based low stress dielectric layer of each of the first memory circuit layer and the plurality of memory circuit layers.

53. The apparatus of claim 52, further comprising a low-stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile formed on the polished or smoothed backside of the of the thinned, substantially flexible monocrystalline semiconductor substrate.

54. The apparatus of claim 49, further comprising a low-stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile formed on the polished or smoothed backside of the of the thinned, substantially flexible monocrystalline semiconductor substrate.

55. The apparatus of claim 46, wherein at least one of:

the memory controller circuit layer, the first memory circuit layer, and the plurality of memory circuit layers together form a memory, the memory being reconfigurable by operation of the memory controller circuit layer;

the memory controller circuit layer further comprises circuitry for performing functional testing of the first memory circuit layer and at least one of the plurality of memory circuit layers;

a process technology used to make the memory controller circuit layer is different from a process technology used to make the first memory circuit layer and the plurality of memory circuit layers.

56. The apparatus of claim 55, further comprising a low-stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile formed on the polished or smoothed backside of the of the thinned, substantially flexible monocrystalline semiconductor substrate.

57. The apparatus of claim 47, further comprising a low-sress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile formed on the polished or smoothed backside of the of the thinned, substantially flexible monocrystalline semiconductor substrate.

58. An apparatus comprising:

a first integrated circuit layer having a thickness Th₁;

a second integrated circuit layer in a stacked relationship with and adjacent to the first integrated circuit layer having a thickness Th₂; and

a plurality of vertical interconnect segments interconnecting the first and second integrated circuit layers, wherein each vertical interconnect segment forms an interconnection only between a pair of adjacent integrated circuits;

wherein the vertical interconnect segments have lengths of Th₁+Th₂ or less; and

wherein at least one of the first integrated circuit and the second integrated circuit is thin and substantially flexible and comprises a thinned, substantially flexible monocrystalline semiconductor substrate of one piece made from a semiconductor wafer thinned from a backside thereof by at least one of abrasion, etching and parting, and subsequently polished or smoothed to form a polished or smoothed surface.

59. The apparatus of claim 58, wherein the first integrated circuit is fabricated using one process technology, and the second integrated circuit is fabricated using a different process technology.

60. The apparatus of claim 58, wherein the at least one of the first integrated circuit layer and the second integrated circuit layer is formed with a low stress dielectric material, wherein the low stress dielectric material is at least one of a silicon dioxide dielectric material and an oxide of silicon dielectric material and has a tensile stress of less than 5×

10⁸ dynes/cm².

61. The apparatus of claim 60, wherein the first integrated circuit and the second integrated circuit are formed with one of single crystal semiconductor material and polycrystalline semiconductor material.

62. The apparatus of claim 60, wherein one of the first and second integrated circuits are formed using a different process technology than another of the first and second integrated circuits, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.

63. The apparatus of claim 60, wherein at least one of the first and second integrated circuits comprises a microprocessor.

64. The apparatus of claim 60, further comprising at least one memory integrated circuit and at least one logic integrated circuit, wherein the at least one logic integrated circuit performs testing of the at least one memory integrated circuit.

65. The apparatus of claim 60, further comprising at least one memory integrated circuit having multiple memory locations including at least one memory location used for sparing, wherein data from the at least one memory location on the at least one memory integrated circuit is used instead of data from a defective memory location on the at least one memory integrated circuit.

66. The apparatus of claim 60, further comprising at least one memory integrated circuit and at least one logic integrated circuit, wherein the at least one logic integrated circuit performs programmable gate line address assignment with respect to the at least one memory integrated circuit.

67. The apparatus of claim 60, wherein the vertical interconnect segments form a plurality of interior vertical interconnections that pass through the thinned, substantially flexible monocrystalline semiconductor substrate and are insulated therefrom by a low-stress silicon-based dielectric material with a tensile stress of less than 5×

10⁸ dynes/cm².

68. The apparatus of claim 60, wherein the vertical interconnect segments form continuous vertical interconnections that pass through the thinned, substantially flexible monocrystalline semiconductor substrate and are insulated therefrom by a low-stress silicon-based dielectric material with a tensile stress of less than 5×

10⁸ dynes/cm² and that connect circuitry of the first and second integrated circuits.

69. The apparatus of claim 60, wherein information processing is performed on data routed between circuitry on the first and second integrated circuits.

70. The apparatus of claim 60, wherein at least one of the integrated circuits comprises reconfiguration circuitry.

71. The apparatus of claim 60, including at least one logic integrated circuit having logic for performing at least one of the following functions:

virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.

72. The apparatus of claim 60, further comprising:

a memory array having a plurality of memory cells, a plurality of data lines, and a plurality of gate lines, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to a gate control signal on one of said gate lines;

circuitry for generating a gate control signal in response to an address, including means for mapping addresses to gate lines; and

a controller for determining that one of said memory cells is defective and for altering said mapping to eliminate references to said one of said memory cells.

73. The apparatus of claim 60, further comprising:

one or more controller integrated circuits;

one or more memory integrated circuits;

a plurality of data lines and a plurality of gate lines on each memory integrated circuit;

an array of memory cells on each memory integrated circuit, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines;

a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines, said address assignments for determining which of said gate lines is selected for each programmed address assignment; and

controller logic for determining that one of said memory cells is defective and for altering, in at least one instance, said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines.

74. The apparatus of claim 73, wherein said controller logic tests said memory cells periodically to determine if any of said memory cells is defective and wherein said controller logic eliminates references in said address assignments to gate lines that cause detected defective memory cells to couple data values to said data lines.

75. The apparatus of claim 73, further comprising programmable logic to prevent the use of data values from data lines when gate lines cause said detected defective memory cells to couple data values to said data lines.

76. The apparatus of claim 73, wherein said memory cells are arranged within physical space in a physical order and are arranged within an address space in a logical order, wherein said physical order of at least one memory cell is different than the logical order of that memory cell.

77. The apparatus of claim 73, wherein external testing of the controller logic together with testing by the controller of the memory cells achieves a functional testing of a preponderance of the memory cells.

78. The apparatus of claim 73, wherein testing by the controller logic of the memory cells substantially reduces or eliminates the need for external testing of the memory cells of the one or more memory integrated circuits.

79. The apparatus of claim 73, wherein altering said address assignments comprises preventing the use of at least one defective gate line and replacing references to memory cells addressed using said defective gate line with references to spare memory cells addressed using a spare gate line.

80. The apparatus of claim 60, wherein the vertical interconnect segments traverse at least one of the first thickness and the second thickness, and wherein the vertical interconnect segments pass through holes formed in the thinned, substantially flexible monocrystalline semiconductor substrate and are insulated therefrom by a low-stress silicon-based dielectric material with a tensile stress of less than 5×

10⁸ dynes/cm².

81. The apparatus of claim 60, wherein the vertical interconnect segments each comprises a conductive land formed on a surface of the first integrated circuit and a conductive land formed on a surface of the second integrated circuit, and wherein the vertical interconnect segments pass through the thinned, substantially flexible monocrystalline semiconductor substrate and are insulated therefrom by a low-stress silicon-based dielectric material with a tensile stress of less than 5×

10⁸ dynes/cm².

82. The apparatus of claim 60, wherein each the vertical interconnect segments comprises a conductive land formed on a surface of the first integrated circuit, a conductive land formed on a surface of the second integrated circuit, and a via formed within one of the first and second integrated circuits, and wherein the vertical interconnect segments pass through the thinned, substantially flexible monocrystalline semiconductor substrate and are insulated therefrom by a low-stress silicon-based dielectric material with a tensile stress of less than 5×

10⁸ dynes/cm².

83. The apparatus of claim 82, wherein the conductive land formed on the surface of the first integrated circuit and the conductive land formed on the surface of the second integrated circuit are bonded together.

84. The apparatus of claim 82, wherein the conductive land formed on the surface of the first integrated circuit and the conductive land formed on the surface of the second integrated circuit are bonded together by thermal diffusion bonding.

85. The apparatus of claim 60, wherein the vertical interconnect segments are grouped to form a dense interconnect array.

86. The apparatus of claim 60, wherein at least one of the integrated circuit layers has a thickness of one of 50 microns or less.

87. The apparatus of claim 60, wherein at least one of the first integrated circuit and the second integrated circuit comprises a monocrystalline semiconductor substrate.

88. The apparatus of claim 60, wherein at least one of said vertical interconnect segments comprises a center portion and a dielectric portion surrounding the center portion, the dielectric portion having tensile stress of less than 5×

10⁸ dynes/cm².

89. The apparatus of claim 60, wherein at least two of the following:

at least one of the plurality of vertical interconnect segments extends through at least one of said integrated circuits and comprises a conductive center portion and a surrounding insulating portion having tensile stress of less than 5×

10⁸ dynes/cm²;

the plurality of vertical interconnect segments are each formed of a first metal contact on the first integrated circuit and a second aligned metal contact on the second integrated circuit bonded together;

the vertical interconnect segments are formed at the time of bonding between the adjacent integrated circuits to interconnect the adjacent integrated circuits;

at least one of the integrated circuits comprises a substrate that is one of a thinned monocrystalline semiconductor substrate and a thinned polycrystalline semiconductor substrate;

at least one of the integrated circuits is formed using a different process technology than another one of the integrated circuits, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance;

at least one of the integrated circuits comprises a microprocessor;

information processing is performed on data routed between the integrated;

at least one of the integrated circuits has reconfiguration circuitry;

at least one of the integrated circuits has logic circuitry formed thereon for performing at least one function from the group consisting of;

virtual memory management, error correcting codes. (ECC), indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.

90. An apparatus comprising:

a first integrated circuit having a thickness Th₁;

a second integrated circuit in a stacked relationship with and adjacent to the first integrated circuit having a thickness Th₂; and

hundreds of vertical interconnect segments interconnecting the first and second integrated circuits including a plurality of vertical interconnect segments having lengths of Th₁+Th₂ or less, wherein the plurality of vertical interconnect segments form interconnections only between a pair of adjacent integrated circuits; and

a low-stress silicon-based dielectric layer having a tensile stress of less than 5×

10⁸ dynes/cm²;

wherein;

a process technology used to make the first integrated circuit is different from a process technology used to make the second integrated circuit;

the first integrated circuit is thin and substantially flexible and comprises a thinned, substantially flexible monocrystalline semiconductor substrate of one piece made from a semiconductor wafer thinned from a backside thereof by at least one of abrasion, etching and parting, and subsequently polished or smoothed to form a polished or smoothed backside surface;

the polished or smoothed surface of the thinned, substantially flexible monocrystalline semiconductor substrate is polished or smoothed to reduce vulnerability to fracture as a result of flexing;

the first integrated circuit has edges that define its size in area, and the thinned, substantially flexible monocrystalline semiconductor substrate extends in one piece across a substantial portion of the area between the edges; and

,

the second integrated circuit comprises an array of memory cells formed with at least one silicon-based dielectric layer having a tensile stress of less than 5×

10⁸ dynes/cm² and without a monocrystalline semiconductor substrate.

91. The apparatus of claim 90, further comprising a low-stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile formed on the polished or smoothed backside surface of the of the thinned, substantially flexible monocrystalline semiconductor substrate.

92. An apparatus comprising:

a first integrated circuit having a thickness Th₁;

a second integrated circuit in a stacked relationship with and adjacent to the first integrated circuit having a thickness Th₂; and

hundreds of vertical interconnect segments interconnecting the first and second integrated circuit including a plurality of vertical interconnect segments having lengths of Th₁+Th₂ or less, wherein the plurality of vertical interconnect segments form interconnections only between a pair of adjacent integrated circuits; and

a low-stress silicon-based dielectric layer having a tensile stress of less than 5×

10⁸ dynes/cm²;

wherein;

a process technology used to make the first integrated circuit is different from a process technology used to make the second integrated circuit;

the first integrated circuit is thin and substantially flexible and comprises a thinned, substantially flexible monocrystalline semiconductor substrate of one piece made from a semiconductor wafer thinned from a backside thereof by at least one of abrasion, etching and parting, and subsequently polished or smoothed to form a polished or smoothed backside surface;

the polished or smoothed surface of the thinned, substantially flexible monocrystalline semiconductor substrate is polished or smoothed to reduce vulnerability to fracture as a result of flexing;

the first integrated circuit has edges that define its size in area, and the thinned, substantially flexible monocrystalline semiconductor substrate extends in one piece across a substantial portion of the area between the edges;

the second integrated circuit comprising an array of non-volatile memory cells formed with at least one silicon-based dielectric layer having a tensile stress of less than 5×

10⁸ dynes/cm²; and

,

the first integrated circuit of the plurality of substantially flexible integrated circuits comprising circuitry for storing a plurality of data bits per memory cell.

93. The apparatus of claim 92, further comprising a low-stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile formed on the polished or smoothed backside surface of the of the thinned, substantially flexible monocrystalline semiconductor substrate.

94. An apparatus comprising:

a first integrated circuit having a thickness Th₁;

a second integrated circuit in a stacked relationship with and adjacent to the first integrated circuit having a thickness Th₂; and

hundreds of vertical interconnect segments interconnecting the first and second integrated circuits including a plurality of vertical interconnect segments having lengths of Th₁+Th₂ or less, wherein the plurality of vertical interconnect segments form interconnections only between a pair of adjacent integrated circuits; and

one or more low-stress silicon-based dielectric layer having a tensile stress of less than 5×

10⁸ dynes/cm²;

wherein;

a process technology used to make the first integrated circuit is different from a process technology used to make the second integrated circuit;

the first integrated circuit is thin and substantially flexible and comprises a thinned, substantially flexible monocrystalline semiconductor substrate of one piece made from a semiconductor wafer thinned from a backside thereof by at least one of abrasion, etching and parting, and subsequently polished or smoothed to form a polished or smoothed backside surface;

the polished or smoothed surface of the thinned, substantially flexible monocrystalline semiconductor substrate is polished or smoothed to reduce vulnerability to fracture as a result of flexing;

the first integrated circuit has edges that define its size in area, and the thinned, substantially flexible monocrystalline semiconductor substrate extends in one piece across a substantial portion of the area between the edges;

the apparatus is substantially flexible based on a combination of low stress of the one or more low-stress dielectric layers and the monocrystalline semiconductor substrate being substantially flexible;

the second integrated circuit comprising an array of non-volatile memory cells formed with at least one silicon-based dielectric layer having a tensile stress of less than 5×

10⁸ dynes/cm²;

the first integrated circuit comprising circuitry for storing a plurality of data bits per memory cell; and

,

the first integrated circuit comprising error correction circuitry for detecting and correcting data read errors from the non-volatile memory cells of the second integrated circuit.

95. The apparatus of claim 94, further comprising a low-stress silicon-based dielectric layer having a stress of less than 5×

10⁸ dynes/cm² tensile formed on the polished or smoothed backside surface of the of the thinned, substantially flexible monocrystalline semiconductor substrate.