Thin film transistor array baseplate

• US 9,263,594 B2
• Filed: 08/20/2012
• Issued: 02/16/2016
• Est. Priority Date: 11/03/2011
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Liu, Xiang, Xue, Jianshe
• Primary Examiner(s): Soward, Ida M
• Application Number:
  US13/701,877
• Publication Number:
  US 20130181222A1
• Time in Patent Office: 1,275 Days
• Field of Search: 257/57, 257/59, 257/66, 257/72, 257/291, 257/E29.117, 257/E29.151, 257/E29.202, 257/E29.273
• US Class Current: 1/1
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs

Abstract

An embodiment of the present invention provides a TFT array substrate including: a base substrate (1) and thin film transistors. The thin film transistor includes a gate electrode (2), a semiconductor layer (5), a semiconductor protective layer, a source electrode (8) and a drain electrode (9). The semiconductor protective layer is disposed adjacent to the semiconductor layer (5) and includes a composite lamination structure, which includes a protective layer formed of an insulating material capable of preventing de-oxygen of the semiconductor layer (5) and an insulating layer formed of an insulating material to be etched more easily.

Claims

1. A thin film transistor (TFT) array substrate comprising:

a base substrate and a thin film transistor functioning as a switching element, the thin film transistor comprising a gate electrode, a semiconductor layer, a semiconductor protective layer, a source electrode and a drain electrode,

wherein the semiconductor protective layer is disposed adjacent to the semiconductor layer and comprises a composite lamination structure, which comprises a protective layer formed of silicon oxide or a metal oxide and being in contact with the semiconductor layer and an insulating layer formed of an organic insulating material.

2. The TFT array substrate according to claim 1, wherein the ratio of thickness of the protective layer to that of the insulating layer is in a range from 1/10 to ⅗

.

3. The TFT array substrate according to claim 2, wherein a thickness of the protective layer is in a range from 300 Å

to 1500 Å

, and a thickness of the insulating layer is in a range from 1000 Å

to 20000 Å

.

4. The TFT array substrate according to claim 1, wherein the protective layer is formed of SiO_x or Al₂O₃, and the insulating layer is formed of an organic resin.

5. The TFT array substrate according to claim 1, further comprising a passivation layer and a transparent pixel electrode.

6. A liquid crystal display comprising the array substrate according to claim 1.

7. The TFT array substrate according to claim 1, wherein the gate electrode is provided on the base substrate, and the semiconductor layer is arranged over the gate electrode.

8. The TFT array substrate according to claim 7, wherein the semiconductor protective layer further comprises a gate insulating composite lamination structure disposed between the gate electrode and the semiconductor layer and adjacent to a lower side of the semiconductor layer, the gate insulating composite lamination structure comprises a gate insulating protective layer formed of silicon oxide or metal oxide and being in contact with the semiconductor layer and a gate insulating layer formed of an organic insulating material.

9. The TFT array substrate according to claim 8, wherein the semiconductor protective layer comprises an etching stop composite lamination structure arranged within the channel and adjacent to a topside of the semiconductor layer, and the etching stop composite lamination structure comprises an etching stop protective layer formed of silicon oxide or metal oxide and being in contact with the semiconductor layer and an etching stop insulating layer formed of an organic insulating material.

10. The TFT array substrate according to claim 7, wherein the source electrode and the drain electrode are arranged on the semiconductor layer, with a channel defined therebetween.

11. The TFT array substrate according to claim 7, wherein the semiconductor protective layer comprises an etching stop composite lamination structure arranged within the channel and adjacent to a topside of the semiconductor layer, and the etching stop composite lamination structure comprises an etching stop protective layer formed of silicon oxide or metal oxide and being in contact with the semiconductor layer and an etching stop insulating layer formed of an organic insulating material.

12. The TFT array substrate according to claim 1, wherein the semiconductor layer is arranged on the base substrate, and the gate electrode is provided on the semiconductor layer.

13. The TFT array substrate according to claim 12, wherein the semiconductor protective layer comprises a buffer insulating composite lamination structure located between the base substrate and the semiconductor layer and adjacent to a lower side of the semiconductor layer, and the buffer insulating composite lamination structure comprises a buffer insulating protective layer formed of silicon oxide or metal oxide and being in contact with the semiconductor layer and an buffer insulating layer formed of an organic insulating material.

14. The TFT array substrate according to claim 13, wherein the source electrode and the drain electrode are arranged on the semiconductor layer, with a channel defined therebetween.

15. The TFT array substrate according to claim 14, wherein the semiconductor protective layer comprises an etching stop composite lamination structure arranged within the channel and adjacent to the topside of the semiconductor layer, and the etching stop composite lamination structure comprises an etching stop protective layer formed of silicon oxide or metal oxide and being in contact with the semiconductor layer and an etching stop insulating layer formed of an organic insulating material.

16. The TFT array substrate according to claim 13, wherein the semiconductor protective layer further comprises an etching stop composite lamination structure arranged within the channel and adjacent to the topside of the semiconductor layer, and the etching stop composite lamination structure comprises an etching stop protective layer formed of silicon oxide or metal oxide and being in contact with the semiconductor layer and an etching stop insulating layer formed of an organic insulating material.