Finfet crosspoint flash memory
First Claim
1. A semiconductor structure comprising:
- a pair of semiconductor fins located on a substrate;
a tunneling gate dielectric located on proximal sidewalls of said pair of semiconductor fins;
a floating gate electrode located between said pair of semiconductor fins and contacting said tunneling gate dielectric, wherein said floating gate electrode fills an entire space between said pair of semiconductor fins;
a control gate dielectric contacting distal sidewalls of said pair of semiconductor fins and a top surface of said floating gate electrode;
a control gate electrode overlying said control gate dielectric;
a back gate dielectric located in said substrate and contacting bottom surfaces of said pair of semiconductor fins; and
a back gate electrode located in said substrate and underlying said back gate dielectric,wherein said tunneling gate dielectric is in contact with portions of a top surface and sidewalls of said back gate dielectric and a top surface of said back gate electrode.
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Accused Products
Abstract
A flash memory device in a dual fin single floating gate configuration is provided. Semiconductor fins are formed on a stack of a back gate conductor layer and a back gate dielectric layer. Pairs of semiconductor fins are formed in an array environment such that shallow trench isolation structures can be formed along the lengthwise direction of the semiconductor fins within the array. After formation of tunneling dielectrics on the sidewalls of the semiconductor fins, a floating gate electrode is formed between each pair of proximally located semiconductor fins by deposition of a conformal conductive material layer and an isotropic etch. A control gate dielectric and a control gate electrode are formed by deposition and patterning of a dielectric layer and a conductive material layer.
16 Citations
19 Claims
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1. A semiconductor structure comprising:
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a pair of semiconductor fins located on a substrate; a tunneling gate dielectric located on proximal sidewalls of said pair of semiconductor fins; a floating gate electrode located between said pair of semiconductor fins and contacting said tunneling gate dielectric, wherein said floating gate electrode fills an entire space between said pair of semiconductor fins; a control gate dielectric contacting distal sidewalls of said pair of semiconductor fins and a top surface of said floating gate electrode; a control gate electrode overlying said control gate dielectric; a back gate dielectric located in said substrate and contacting bottom surfaces of said pair of semiconductor fins; and a back gate electrode located in said substrate and underlying said back gate dielectric, wherein said tunneling gate dielectric is in contact with portions of a top surface and sidewalls of said back gate dielectric and a top surface of said back gate electrode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A semiconductor structure comprising:
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a pair of semiconductor fins located on a substrate; a tunneling gate dielectric located on proximal sidewalls of said pair of semiconductor fins; a floating gate electrode located between said pair of semiconductor fins and contacting said tunneling gate dielectric, wherein said floating fate electrode fills an entire space between said pair of semiconductor fins; a control gate dielectric contacting distal sidewalls of said pair of semiconductor fins and a top surface of said floating gate electrode; a control gate electrode overlying said control gate dielectric; a fin cap structure atop each semiconductor fin in said pair of semiconductor fins, wherein said control gate dielectric contacts sidewalls and a top surface of said fin cap; and a back gate dielectric located in said substrate and contacting bottom surfaces of said pair of semiconductor fins; and a back gate electrode located in said substrate and underlying said back gate dielectric. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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Specification