Manufacturing method of low temperature poly-silicon TFT array substrate

• US 9,349,759 B2
• Filed: 09/24/2014
• Issued: 05/24/2016
• Est. Priority Date: 05/27/2011
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Ma, Zhanjie
• Primary Examiner(s): Lee, Jae
• Application Number:
  US14/495,039
• Publication Number:
  US 20150011055A1
• Time in Patent Office: 608 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 27/1274 using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate

Abstract

A manufacturing method of an LTPS-TFT array substrate is provided. The exemplary method comprises a step of sequentially forming a poly-silicon layer and a data-line-metal layer on a base substrate, and performing a patterning process by using a third mask to simultaneously form an active layer and source and drain electrodes, the active layer being provided on the gate insulating layer and corresponding to the gate electrode, and the source and drain electrodes being provided on the active layer.

Claims

1. A manufacturing method of a low temperature poly-silicon thin film transistor (LTPS-TFT) array substrate, comprising:

Step 1 of depositing a gate-metal-layer on a base substrate, and performing a first patterning process by using a first mask to form a gate electrode;

Step 2 of depositing a gate insulating layer on the base substrate after Step 1, the gate insulating layer covering the base substrate and the gate electrode;

Step 3 of sequentially forming a poly-silicon layer and a data-line-metal layer on the base substrate after Step 2, and performing a third patterning process by using a third mask to form an active layer and source and drain electrodes, the active layer being provided on the gate insulating layer and corresponding to the gate electrode, the source and drain electrodes being provided on the active layer; and

Step 4 of depositing a transparent conductive layer on the base substrate after Step 3, and performing a fourth patterning process by using a fourth mask to form a pixel electrode, the pixel electrode being provided directly on the drain electrode and the gate insulating layer;

wherein the manufacturing method further comprises;

forming a test line in gate-metal-layer by using the first mask in Step 1;

forming a contact hole in the gate insulating layer by using a second mask in Step 2; and

forming a test line in data-line-metal layer by using the third mask in Step 3, the active layer formed in Step 3 filling in the contact hole so that the test line in gate-metal-layer and the test line in data-line-metal layer are capable of being connected with each other.

2. The manufacturing method according to claim 1, further comprising:

Step 5 of depositing a protection layer on the base substrate after Step 4, and forming a via hole in the protection layer by using a fifth mask to expose the pixel electrode.

3. The manufacturing method according to claim 1, further comprising:

forming a test line in gate-metal-layer by using the first mask in Step 1;

forming a contact hole in the gate insulating layer by using a second mask in Step 2;

forming a test line in data-line-metal layer by using the third mask in Step 3; and

filling the contact hole with the transparent conductive layer in Step 4 so that the test line in gate-metal-layer and the test line in data-line-metal layer are connected with each other.

4. The manufacturing method according to claim 1, wherein the third mask is a half-tone or gray-tone mask.

5. The manufacturing method according to claim 1, further comprising:

prior to Step 1, forming a buffer layer on the base substrate.

6. The manufacturing method according to claim 1, wherein forming the poly-silicon layer in Step 3 comprises:

depositing an amorphous silicon layer on the base substrate, and

crystallizing the amorphous silicon layer into the poly-silicon layer by using a crystallizing method.