Manufacturing method of low temperature poly-silicon TFT array substrate

  • US 9,349,759 B2
  • Filed: 09/24/2014
  • Issued: 05/24/2016
  • Est. Priority Date: 05/27/2011
  • Status: Active Grant
First Claim
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1. A manufacturing method of a low temperature poly-silicon thin film transistor (LTPS-TFT) array substrate, comprising:

  • Step 1 of depositing a gate-metal-layer on a base substrate, and performing a first patterning process by using a first mask to form a gate electrode;

    Step 2 of depositing a gate insulating layer on the base substrate after Step 1, the gate insulating layer covering the base substrate and the gate electrode;

    Step 3 of sequentially forming a poly-silicon layer and a data-line-metal layer on the base substrate after Step 2, and performing a third patterning process by using a third mask to form an active layer and source and drain electrodes, the active layer being provided on the gate insulating layer and corresponding to the gate electrode, the source and drain electrodes being provided on the active layer; and

    Step 4 of depositing a transparent conductive layer on the base substrate after Step 3, and performing a fourth patterning process by using a fourth mask to form a pixel electrode, the pixel electrode being provided directly on the drain electrode and the gate insulating layer;

    wherein the manufacturing method further comprises;

    forming a test line in gate-metal-layer by using the first mask in Step 1;

    forming a contact hole in the gate insulating layer by using a second mask in Step 2; and

    forming a test line in data-line-metal layer by using the third mask in Step 3, the active layer formed in Step 3 filling in the contact hole so that the test line in gate-metal-layer and the test line in data-line-metal layer are capable of being connected with each other.

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