Trench-based power semiconductor devices with increased breakdown voltage characteristics

• US 9,391,193 B2
• Filed: 02/23/2015
• Issued: 07/12/2016
• Est. Priority Date: 12/08/2008
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Yedinak, Joseph A., Challa, Ashok, Kinzer, Daniel M., Probst, Dean E., Calafut, Daniel
• Primary Examiner(s): Sefer, A.
• Application Number:
  US14/628,989
• Publication Number:
  US 20150194521A1
• Time in Patent Office: 505 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/0611 for increasing or controlling the breakdown voltage of reverse biased devices H01L29/0661 takes precedence
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

Claims

1. A semiconductor device comprising:

a plurality of trenches extending into a semiconductor region, each of the plurality of trenches having a gate electrode and a shield electrode disposed therein;

a plurality of mesas interleaved between the plurality of trenches;

a plurality of portions of a polysilicon gate runner disposed over the plurality of trenches making electrical contact with the gate electrodes disposed in each of the plurality of trenches, and electrically isolated from the plurality of mesas;

a metal gate runner having a plurality of portions in contact with plurality of portions of the polysilicon gate runner, and

a plurality of p-well diffusions included in the plurality of mesas.

2. The semiconductor device of claim 1, wherein the plurality of portions of the metal gate runner are separated by a plurality of dielectric portions.

3. The semiconductor device of claim 1, wherein the plurality of portions of the polysilicon gate runner are aligned perpendicular to the plurality of trenches.

4. The semiconductor device of claim 1, wherein the metal gate runner is disposed above the plurality of portions of the polysilicon gate runner.

5. The semiconductor device of claim 1, wherein the plurality of p-well diffusions included in the plurality of mesas are disposed below the metal gate runner.

6. The semiconductor device of claim 1, wherein the plurality of p-well diffusions included in the plurality of mesas are configured to be at a floating potential or a fixed potential.

7. The semiconductor device of claim 1, wherein a portion of plurality of trenches are disposed in a device region of the semiconductor device, the metal gate runner and the polysilicon gate runner are disposed in a connection region of the semiconductor device.

8. The semiconductor device of claim 1, wherein the plurality of trenches is a first plurality of trenches,

the semiconductor device further comprising:

a second plurality of trenches each including a shield electrode disposed therein and each excluding a gate electrode, at least one of the second plurality of trenches being grounded or floating.

9. The semiconductor device of claim 1, wherein a first trench from the plurality of trenches includes a gate electrode having a width less than a width of a gate electrode including a second trench from the plurality of trenches.

10. A semiconductor device comprising:

a trench extending into a semiconductor region, the trench having a gate electrode and a shield electrode disposed therein;

a mesa adjacent to the trench;

a segment of a polysilicon gate runner disposed over the trench and making electrical contact with the gate electrode, and electrically isolated from the mesa;

a metal gate runner having a portion in contact with the segment of the polysilicon gate runner; and

a p-well diffusion included in the mesa.

11. The semiconductor device of claim 10, wherein the metal gate runner is adjacent to a dielectric portion.

12. The semiconductor device of claim 10, wherein the metal gate runner is aligned perpendicular to trench.

13. The semiconductor device of claim 10, wherein the metal gate runner is disposed above the segment of the polysilicon gate runner.

14. The semiconductor device of claim 10, wherein the p-well diffusion included in the mesa is disposed below the metal gate runner.

15. The semiconductor device of claim 10, wherein the p-well diffusion included in the mesa is configured to be at a floating potential or a fixed potential.

16. The semiconductor device of claim 10, wherein the p-well diffusion included in the mesa terminates before an end of the trench.

17. The semiconductor device of claim 10, wherein the trench is a first trench,

the semiconductor device including:

a second trench disposed in a device region of the semiconductor device, the metal gate runner and the segment of the polysilicon gate runner being disposed in a connection region of the semiconductor device.

18. The semiconductor device of claim 10, wherein the trench is a first trench,

the semiconductor device further comprising:

a second trench including a shield electrode disposed therein and excluding a gate electrode, the second trench being grounded or floating.