System for increasing utilization of storage media

• US 9,424,180 B2
• Filed: 02/10/2014
• Issued: 08/23/2016
• Est. Priority Date: 04/17/2009
• Status: Active Grant

• Current Assignee: Innovations In Memory LLC
• Original Assignee: Violin Memory Incorporated
• Inventors: de la Iglesia, Erik
• Primary Examiner(s): OBERLY, ERIC T
• Application Number:
  US14/176,326
• Publication Number:
  US 20150032942A1
• Time in Patent Office: 925 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/2094 Redundant storage or storage space G06F11/2056 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0683 Plurality of storage devices

Abstract

A storage system creates an abstraction of flash Solid State Device (SSD) media allowing random write operations of arbitrary size by a user while performing large sequential write operations of a uniform size to an SSD array. This reduces the number of random write operations performed in the SSD array and as a result increases performance of the SSD array. A control element determines when blocks from different buffers should be combined together or discarded based on fragmentation and read activity. This optimization scheme increases memory capacity and improves memory utilization and performance.

Claims

1. An apparatus, comprising:

a storage media having a plurality of buffer regions configured to store copies of data stored in a storage array;

a staging buffer configured to buffer the data for different write operations;

a processor configured to aggregate together the data in the staging buffer from the different write operations and store the aggregated data into blocks of a buffer region of the plurality of buffer regions of the storage media;

wherein the processor is further configured to discard data in blocks of the buffer region having a minimum read count when a number of buffer regions currently being used is below a first threshold number and discard data in the buffer regions according the a ranking of buffer regions when the number of buffer regions currently being used is above a threshold.

2. The apparatus of claim 1, an indirection table configured to map the aggregated data from the write operations to different block regions within a same one of the buffer regions;

wherein the write operations are each allocated indirection entries within the indirection table and the indirection entries include device identifiers for storage devices in the storage media and physical addresses of the block regions where the data is stored in the storage media.

3. The apparatus of claim 1, wherein a size of the buffer regions and a size of the block regions are configurable.

4. The apparatus of claim 3, wherein the processor is configured to select the size of the buffer regions to increase write throughput to the storage media.

5. The apparatus of claim 1, wherein the processor is configured to aggregate different groups of data for different groups of write operations into a staging buffer and write the different aggregated groups of data from the staging buffer into associated buffer regions within the storage media.

6. The apparatus of claim 1, wherein the indirection table maps random addresses of the write operations into continuous block address locations within the buffer regions.

7. The apparatus of claim 1, wherein the storage media comprises an array of Solid State Devices (SSDs).

8. The apparatus of claim 1, wherein the processor is configured to discard data from the buffer regions and replace the data discarded from the buffer regions with other data from the storage array.

9. The apparatus of claim 8, further comprising block counters containing block count values identifying a number of the block regions in the different buffer regions containing valid data, wherein the processor is configured to discard data from the buffer regions or aggregate data from the different buffer regions together into a same one of the buffer regions according to the block count values.

10. The apparatus according to claim 1, further comprising bit maps for each of the buffer regions, where bits in the bit maps identify a used or unused status for data within associated block regions within buffer regions, and the processor is further configured to combine data from the different buffer regions together into a same one of the buffer regions according to the bit maps.