Memory devices having source lines directly coupled to body regions and methods

• US 9,484,100 B2
• Filed: 06/09/2014
• Issued: 11/01/2016
• Est. Priority Date: 01/21/2011
• Status: Active Grant

• Current Assignee: Lodestar Licensing Group LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Goda, Akira
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US14/299,813
• Publication Number:
  US 20140286106A1
• Time in Patent Office: 876 Days
• Field of Search: 365/185.29, 365/185.18, 365/185.17
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. Configurations and methods shown should provide a reliable bias to a body region for memory operations such as erasing.

Claims

1. A method of operating a memory device, the method comprising:

biasing a data line to a first potential, where the data line is coupled to a first end of a first string of memory cells and to a first end of a second string of memory cells;

biasing a source to a second potential substantially the same as the first potential, where the source is coupled to a second end of the first string and to a second end of the second string of memory cells;

deactivating a select gate coupled between the first end of the second string of memory cells and the data line; and

performing a programming operation on a selected memory cell of the first string of memory cells concurrently with biasing the data line to the first potential and the source to the second potential and while the select gate is deactivated.

2. The method of claim 1, wherein the select gate comprises a first select gate and further comprising activating a second select gate concurrently with performing the programming operation, wherein the second select gate is coupled between the first end of the first string of memory cells and the data line.

3. The method of claim 2, wherein activating the second select gate further comprises activating the second select gate by biasing a control gate of the second select gate to a third potential where the third potential is greater than the first potential.

4. The method of claim 3, further comprising deactivating a third and a fourth select gate concurrently with performing the programming operation, wherein the third select gate is coupled between the second end of the second string of memory cells and the source, and where the fourth select gate is coupled between the second end of the first string of memory cells and the source.

5. The method of claim 3, further comprising biasing unselected memory cells of the first string of memory cells to a fourth potential sufficient to activate the unselected memory cells concurrently with performing the programming operation.

6. The method of claim 1, wherein performing a programming operation on a selected memory cell further comprises performing a programming operation by applying a programming potential to a control gate of the selected memory cell to increase a threshold voltage of the selected memory cell.

7. A method of operating an array of memory cells, the method comprising:

applying a potential to a data line, where the data line is coupled to a first end of a first string of memory cells and to a first end of a second string of memory cells;

applying substantially the same potential to a source, where the source is coupled to a second end of the first string of memory cells and to a second end of the second string of memory cells;

activating a first select gate coupled between the first end of the first string of memory cells and the data line;

deactivating a second select gate coupled between the first end of the second string of memory cells and the data line; and

applying a programming potential to a selected memory cell of the first string of memory cells configured to increase a threshold voltage of the selected memory cell;

wherein the programming potential is applied concurrently with applying substantially the same potential to the data line and source and with activating the first select gate and deactivating the second select gate.

8. The method of claim 7, wherein the potential applied to the data line is less than a potential applied to the first select gate to activate the first select gate.

9. The method of claim 7, further comprising reading a selected memory cell of the first string of memory cells, wherein the data line is biased to approximately 0.5 volts and the source is biased to approximately zero volts, a selected memory cell gate is biased to a read voltage, and unselected memory cell gates are biased to a pass voltage.

10. The method of claim 9, wherein the read voltage is between zero and four volts depending on a program state being read.

11. The method of claim 10, wherein the pass voltage is approximately six volts.