Thin film transistor array substrate, manufacturing method thereof, and display device

• US 9,530,807 B2
• Filed: 12/10/2012
• Issued: 12/27/2016
• Est. Priority Date: 05/11/2012
• Status: Active Grant

• Current Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.)
• Original Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.)
• Inventors: Li, Tiansheng, Zhang, Wenyu, Xie, Zhenyu
• Primary Examiner(s): Ho, Anthony
• Assistant Examiner(s): QUINTO, KEVIN V
• Application Number:
  US13/993,666
• Publication Number:
  US 20140061645A1
• Time in Patent Office: 1,478 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G02F 1/133707 Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
• CPC Class Codes: G02F 1/134318 having a patterned common electrode
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 33/36 characterised by the electrodes

Abstract

A thin film transistor (TFT) array substrate, a manufacturing method thereof and a display device are provided. The manufacturing method comprises: forming a first passivation layer (8) on a substrate (1), and forming a board wiring PAD-region via hole (11) in the first passivation layer (8) above the board wiring PAD region (11) through a first patterning process; forming a second passivation layer (16) on the substrate (1) formed with the board wiring PAD-region via hole (11), and forming a pixel-region via hole (15) in the first passivation layer (8) and the second passivation layer (16) above the display electrode (7) through a second patterning process in such a way that the pixel-region via hole (15) has a top-size smaller than its bottom-size; and applying a transparent conductive layer on the substrate (1) formed with the pixel-region via hole (15) to form a second display electrode.

Claims

1. A manufacturing method of a thin film transistor array substrate, comprising:

forming a first passivation layer on a substrate formed with a gate scan line, a thin film transistor, a data line, a first display electrode and a board wiring PAD region, and forming a board wiring PAD-region via hole in the first passivation layer above the board wiring PAD region through a first patterning process;

forming a second passivation layer on the substrate formed with the board wiring PAD-region via hole, and forming a pixel-region via hole in the first passivation layer and the second passivation layer above the first display electrode through a second patterning process in such a way that the pixel-region via hole has a top-size smaller than its bottom-size; and

applying a transparent conductive layer on the substrate formed with the pixel-region via hole to form a second display electrode,

wherein the pixel-region via hole is formed at a region other than the thin film transistor, and

wherein, for cross sections of the pixel-region via hole taken along a direction parallel to the substrate, an area of cross sections away from the substrate is smaller than an area of cross sections closer to the substrate.

2. The method according to claim 1, wherein, as seen in a plan view, the pixel-region via hole is in a strip-shape extending along at least one direction;

and

wherein a cross-section of the pixel-region via hole perpendicular to the extending direction of the strip-shape has a shape of a regular trapezoid with an upper-base smaller than its lower-base.

3. The method according to claim 2, wherein in the step of applying the transparent conductive layer on the substrate formed with the pixel-region via hole, the transparent conductive layer is discontinued at a location of the pixel-region via hole, so as to form the second display electrode having a slit-structure.

4. The method according to claim 1, wherein the first display electrode is a pixel electrode, and the second display electrode is a common electrode.

5. The method according to claim 1, wherein the cross-section of the PAD-region via hole, taken along a direction perpendicular to a surface of the substrate, has a shape of an inverted trapezoid with an upper-base larger than its lower-base.

6. The method according to claim 1, wherein the step of forming the board wiring PAD-region via hole through the first patterning process comprises:

applying photoresist on the first passivation layer, exposing with a first mask, and performing a developing processing; and

etching the first passivation layer not covered with the photoresist by a dry etch method, so that the board wiring PAD-region via hole is formed.

7. The method according to claim 6, wherein in the second patterning process, the second passivation layer above the board wiring PAD-region via hole further has a via hole formed therein.

8. The method according to claim 1, wherein the step of forming the pixel-region via hole through the second patterning process comprises:

applying photoresist on the second passivation layer, exposing with a second mask, and performing a developing processing; and

etching the second passivation layer not covered with the photoresist and the first passivation layer therebelow by a dry etch method, so that the pixel-region via hole are formed.

9. The method according to claim 1, wherein a depth of the pixel-region via hole is less than or equal to a sum of a thicknesses of the first passivation layer and a thickness of the second passivation layer.

10. The method according to claim 1, wherein in the second patterning process, an etching rate of the second passivation layer is less than an etching rate of the first passivation layer.

11. The method according to claim 10, wherein a formation temperature of the second passivation layer is lower than that of the first passivation layer.

12. The method according to claim 1, wherein a procedure of forming the gate scan line, the thin film transistor, the data line, the first display electrode and the board wiring PAD region comprises:

forming a gate electrode of the thin film transistor, the gate scan line, and the board wiring PAD region on the substrate;

forming a semiconductor active layer, the data line, and a source electrode and a drain electrode of the thin film transistor on the substrate formed with the gate electrode; and

forming the first display electrode on the substrate formed with the source electrode and the drain electrode.

13. The method according to claim 1, wherein a procedure of forming the gate scan line, the thin film transistor, the data line, the first display electrode and the board wiring PAD region comprises:

forming a gate electrode of the thin film transistor, the gate scan line, and the board wiring PAD region on the substrate;

forming a semiconductor active layer on the substrate formed with the gate electrode;

on the substrate formed with the semiconductor active layer, forming the first display electrode; and

forming the data line, and a source electrode and a drain electrode of the thin film transistor on the substrate formed with the first display electrode.