Thin film transistor array substrate, manufacturing method thereof, and display device

  • US 9,530,807 B2
  • Filed: 12/10/2012
  • Issued: 12/27/2016
  • Est. Priority Date: 05/11/2012
  • Status: Active Grant
First Claim
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1. A manufacturing method of a thin film transistor array substrate, comprising:

  • forming a first passivation layer on a substrate formed with a gate scan line, a thin film transistor, a data line, a first display electrode and a board wiring PAD region, and forming a board wiring PAD-region via hole in the first passivation layer above the board wiring PAD region through a first patterning process;

    forming a second passivation layer on the substrate formed with the board wiring PAD-region via hole, and forming a pixel-region via hole in the first passivation layer and the second passivation layer above the first display electrode through a second patterning process in such a way that the pixel-region via hole has a top-size smaller than its bottom-size; and

    applying a transparent conductive layer on the substrate formed with the pixel-region via hole to form a second display electrode,wherein the pixel-region via hole is formed at a region other than the thin film transistor, andwherein, for cross sections of the pixel-region via hole taken along a direction parallel to the substrate, an area of cross sections away from the substrate is smaller than an area of cross sections closer to the substrate.

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