Semiconductor memory device

• US 9,659,663 B2
• Filed: 03/12/2015
• Issued: 05/23/2017
• Est. Priority Date: 09/16/2014
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Futatsuyama, Takuya, Hosono, Koji, Shirakawa, Masanobu
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): Techane, Muna A
• Application Number:
  US14/645,740
• Publication Number:
  US 20160078954A1
• Time in Patent Office: 803 Days
• Field of Search: 365 72
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line coupled to the first memory cell; and a second word line coupled to the second memory cell. When data is read from the first memory cell, a first voltage and a second voltage is applied to the first word line. A voltage of the second word line changes a first number of times while the first voltage is applied to the first word line, and the voltage changes a second number of times different from the first number of times while the second voltage is applied to the first word line.

Claims

1. A semiconductor memory device comprising:

a first memory cell;

a second memory cell adjacent to the first memory cell;

a first word line coupled to the first memory cell; and

a second word line coupled to the second memory cell,

wherein when data is read from the first memory cell,

a first voltage and a second voltage different from the first voltage are applied to the first word line,

a voltage applied to the second word line changes a first number of times while the first voltage is applied to the first word line, and the voltage applied to the second word line changes a second number of times different from the first number of times while the second voltage is applied to the first word line,

the first voltage is lower than the second voltage, and

the first voltage of times is larger than the second number of times.

2. The device according to claim 1, wherein the second voltage is applied to the first word line subsequent to the first voltage.

3. The device according to claim 1, wherein the first voltage is applied to the first word line subsequent to the second voltage.

4. The device according to claim 1, further comprising:

a third memory cell coupled to the first word line;

a fourth memory cell adjacent to the third memory cell, the third memory cell being coupled to the second word line, wherein

when the data held in the first memory cell is read, data held in the third memory cell is also read,

data read from the first memory cell at a time when the voltage applied to the second word line is changed a third number of times is fetched in a sense amplifier,

data read from the third memory cell at a time when the voltage applied to the second word line is changed a fourth number of times is fetched in the sense amplifier,

the third number of times is different from the fourth number of times,

data is read from the second and fourth memory cells before the first and second voltages are applied to the first word line,

the third number of times depends on the data read from the second memory cell, and

the fourth number of times depends on the data read from the fourth memory cell.

5. The device according to claim 1, wherein in a program-verification operation of the first memory cell,

a voltage applied to the first word line and a voltage applied to the second word line are changed more than once.

6. The device according to claim 5, wherein in the program-verification operation, the voltages applied to the first word line and the second word line are changed the same number of times.

7. The device according to claim 6, further comprising:

a third memory cell adjacent to the second memory cell; and

a third word line coupled to the third memory cell,

wherein in the program-verification operation, of the first memory cell, at a time, the voltage applied to the second word line is higher than the voltage applied to the first word line, and

wherein in the program-verification operation of the first memory cell, a fifth voltage is applied to the third work line, and a maximum voltage applied to the second word line is less than or equal to the fifth voltage.

8. The device according to claim 1, wherein

a data read operation of the first memory cell includes a first read operation and a second read operation,

in the first read operation, a third voltage lower than the first voltage and a fourth voltage lower than the second voltage are applied to the first word line and a constant voltage is applied to the second word line, and

in the second read operation, the first and second voltages are applied to the first word line and the voltage of the second word line is changed.

9. The device according to claim 1, further comprising:

a third memory cell; and

a third word line coupled to the third memory cell, wherein

the first word line is arranged between the second word line and the third word line,

data is read from the second and third memory cells before the first and second voltages are applied to the first word line, and

a voltage applied to the third word line changes a third number of times different from the first number of times and the second number of times while the first voltage is applied to the first word line.

10. The device according to claim 9, wherein the first voltage is for determining whether a threshold voltage of the first memory cell is in an erase level.

11. The device according to claim 1, wherein

the first and second word lines are stacked, and

the voltage of the second word line depends on a layer position in which the second word line is provided.

12. The device according to claim 1, further comprising:

a bit line electrically coupled to the second memory cell;

a sense amplifier coupled to the bit line;

a first block including the first and second memory cells; and

a second block discharging the bit line, wherein

the first block is arranged between the sense amplifier and the second block, and

the bit line is discharged by the sense amplifier and the second block after a data read operation.

13. The device according to claim 1, wherein when a threshold level of the second memory cell is higher than that of the first memory cell, the voltage of the second word line is controlled to correct a threshold voltage of the first memory cell.

14. The device according to claim 13, wherein when the threshold level of the second memory cell is the same as that of the first memory cell, the voltage of the second word line is controlled to correct the threshold voltage of the first memory cell.

19. The device according to claim 1, wherein the second memory cell on a source side is adjacent to the first memory cell on a drain side.

20. The device according to claim 19, further comprising:

a third memory cell on the drain side adjacent to the first memory cell on the source side; and

a third word line coupled to the third memory cell,

wherein while the first voltage is applied to the first word line and while the second voltage is applied to the first word line, a voltage to switch on the third memory cell regardless of held data of the third memory cell is applied to the third word line.

15. A semiconductor memory device comprising:

a first memory cell;

a second memory cell coupled to the first memory cell;

a first word line coupled to the first memory cell; and

a second word line coupled to the second memory cell,

wherein in a program-verification operation of the first memory cell,

a voltage applied to the first word line changes a first number of times, and a voltage applied to the second word line changes a second number of times.

16. The device according to claim 15, wherein the first number of times is the same as the second number of times.

17. The device according to claim 16, wherein at a time, the voltage of the second word line is higher than the voltage of the first word line.

18. The device according to claim 15, wherein when data is read from the first memory cell,

a second voltage and a third voltage different from the second voltage are applied to the first word line, and

the voltage applied to the second word line changes a third number of times while the second voltage is applied to the first word line, and the voltage applied to the second word line changes a fourth number of times different from the third number of times while the third voltage is applied to the first word line.