Array substrate and method of fabricating the same, and display device

• US 9,711,539 B2
• Filed: 07/17/2015
• Issued: 07/18/2017
• Est. Priority Date: 10/31/2014
• Status: Active Grant

• Current Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Inventors: Liu, Chong, Ma, Haitao, Liu, Huanping, Zhao, Haisheng, Xiao, Hongxi, Peng, Zhilong
• Primary Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US14/802,668
• Publication Number:
  US 20160126261A1
• Time in Patent Office: 732 Days
• CPC Class Codes: H01L 27/1244 for preventing breakage, peeling or short circuiting

Abstract

The present invention provides an array substrate, a method of fabricating the array substrate, and a display device. The method of fabricating the array substrate of the present invention comprises steps of: sequentially forming a first transparent conductive film and a source-drain metal film on a substrate; forming a source-drain metal pattern by performing a patterning process on the source-drain metal film; forming a pattern comprising a pixel electrode and a compensation structure that is provided below the source-drain metal pattern by performing a patterning process on the first transparent conductive film.

Claims

1. An array substrate, comprising:

a pixel electrode and a compensation structure provided in the same layer above a substrate, the compensation structure comprising transparent conductive material; and

a source-drain metal pattern provided on the compensation structure;

wherein the compensation structure is configured to compensate for a height difference at a turning point of the source-drain metal pattern.

2. The array substrate of claim 1, wherein the source-drain metal pattern comprises at least a source, a drain, and a data line.

3. The array substrate of claim 2, wherein between the substrate and the pixel electrode, the array substrate further comprises:

a gate metal pattern provided above the substrate;

a gate insulation layer provided on the gate metal pattern; and

an active layer provided on the gate insulation layer.

4. The array substrate of claim 3, further comprising an ohmic contact layer provided on the active layer and between the source and the drain, wherein the source and the drain are electrically connected to the active layer through the ohmic contact layer, respectively.

5. The array substrate of claim 4, further comprising:

a planarization layer; and

a common electrode provided on the planarization layer.

6. The array substrate of claim 3, wherein the gate metal pattern comprises at least a gate, a gate line, and a gate metal connecting line.

7. A display device, comprising an array substrate, the array substrate comprising:

a pixel electrode and a compensation structure provided in the same layer above a substrate, the compensation structure comprising transparent conductive material; and

a source-drain metal pattern provided on the compensation structure;

wherein the compensation structure is configured to compensate for a height difference at a turning point of the source-drain metal pattern.

8. The display device of claim 7, wherein the source-drain metal pattern comprises at least a source, a drain, and a data line.

9. The display device of claim 8, wherein between the substrate and the pixel electrode, the array substrate further comprises:

a gate metal pattern provided above the substrate;

a gate insulation layer provided on the gate metal pattern; and

an active layer provided on the gate insulation layer.

10. The display device of claim 9, further comprising an ohmic contact layer provided on the active layer and between the source and the drain, wherein the source and the drain are electrically connected to the active layer through the ohmic contact layer, respectively.

11. The display device of claim 10, further comprising:

a planarization layer; and

a common electrode provided on the planarization layer.

12. The display device of claim 9, wherein the gate metal pattern comprises at least a gate, a gate line, and a gate metal connecting line.