Addressing, command protocol, and electrical interface for non-volatile memories utilized in recording usage counts

  • US 9,837,136 B2
  • Filed: 12/28/2015
  • Issued: 12/05/2017
  • Est. Priority Date: 06/16/2005
  • Status: Active Grant
First Claim
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1. A memory module, comprising:

  • a plurality of memory cells; and

    a plurality of signal lines for communicating with a processing device, the memory module configured such that upon encountering a busy condition while processing a command received by the memory module, the memory module limits a voltage on a first signal line of the plurality of signal lines for a period of time to be no more than an intermediate voltage greater than voltage levels corresponding to a binary zero state and less than voltage levels corresponding to a binary one state when voltages on the first signal line is not limited by the memory module, for indicating an occurrence of the busy condition,wherein the memory module is configured to receive a clock signal on the first signal line, and during the period of time in which the memory modules limits a voltage on the first signal line of the plurality of signal lines to be no more than the intermediate voltage, the memory module

         1) receives the clock signal on the first signal line and

         2) at the same time indicates to the processing device the occurrence of the busy condition by limiting the voltage on the first signal line to be no more than the intermediate voltage.

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