Semiconductor device and method for fabricating the same

• US 9,922,974 B2
• Filed: 07/05/2017
• Issued: 03/20/2018
• Est. Priority Date: 08/28/2015
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Hsu, Chia Chang, Lin, Chun-Hsien
• Primary Examiner(s): Mandala, Michelle
• Application Number:
  US15/641,336
• Publication Number:
  US 20170301670A1
• Time in Patent Office: 258 Days
• Field of Search: None
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02592 amorphous
• CPC Class Codes: H01L 21/76819 Smoothing of the dielectric planarisation of insulating materials per se H01L21/31051
• CPC Class Codes: H01L 21/76853 characterized by particular after-treatment steps
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A method for fabricating semiconductor device includes the steps of: providing a substrate having a gate structure thereon; forming a silicon layer on the substrate to cover the gate structure entirely; planarizing the silicon layer; and performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate.

Claims

1. A method for fabricating semiconductor device, comprising:

providing a substrate having a gate structure thereon;

forming an epitaxial layer adjacent to two sides of the gate structure;

forming a silicon layer on the substrate to cover the gate structure entirely;

planarizing the silicon layer;

performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate; and

removing part of the silicon layer adjacent to one side of the gate structure to expose the epitaxial layer after performing the RMG process.

2. The method of claim 1, wherein the silicon layer comprises an amorphous silicon layer.

3. The method of claim 1, further comprising forming a liner on the substrate and the gate structure before forming the silicon layer.

4. The method of claim 3, wherein the liner comprises silicon oxide or silicon nitride.

5. The method of claim 1, further comprising:

forming a spacer adjacent to the gate structure;

forming a source/drain region in the substrate adjacent to the spacer; and

forming the silicon layer to cover the gate structure and the spacer.

6. The method of claim 5, further comprising:

removing part of the silicon layer adjacent to the gate structure after planarizing the silicon layer to form a contact hole; and

forming a first contact plug in the contact hole.

7. The method of claim 6, wherein the first contact plug contacts the spacer directly.

8. The method of claim 6, further comprising:

forming an interlayer dielectric (ILD) layer on the silicon layer, the gate structure, and the first contact plug; and

forming a second contact plug in the ILD layer and electrically connect to the first contact plug.