3D semiconductor device and structure

• US 9,941,275 B2
• Filed: 03/27/2017
• Issued: 04/10/2018
• Est. Priority Date: 12/29/2012
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Cronquist, Brian, Sekar, Deepak
• Primary Examiner(s): Nicely, Joseph C
• Assistant Examiner(s): JEAN BAPTISTE, WILNER
• Application Number:
  US15/470,872
• Publication Number:
  US 20170200716A1
• Time in Patent Office: 379 Days
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

An Integrated Circuit device, including: a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single crystal transistors, where the second layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of the first transistors that cross the first dice lane, where a plurality of the second transistors are circumscribed by a second dice lane of at least 10 microns width, and there are no second conductive connections to the plurality of the second transistors that cross the second dice lane, and at least one thermal conducting path from at least one of the second single crystal transistors to an external surface of the device.

Claims

1. An Integrated Circuit device, comprising:

a first layer comprising first single crystal transistors;

a second layer overlaying said first layer, said second layer comprising second single crystal transistors,

wherein said second layer thickness is less than one micron,

wherein a plurality of said first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to said plurality of said first transistors that cross said first dice lane,

wherein a plurality of said second transistors are circumscribed by a second dice lane of at least 10 microns width, and there are no second conductive connections to said plurality of said second transistors that cross said second dice lane, and

wherein said second dice lane is overlaying and aligned to said first dice lane; and

at least one thermal conducting path from at least one of said second single crystal transistors to an external surface of said device.

2. An Integrated Circuit device, comprising:

a first layer comprising first single crystal transistors;

a second layer overlaying said first layer, said second layer comprising second single crystal transistors,

wherein said second layer thickness is less than one micron,

wherein a plurality of said first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to said plurality of said first transistors that cross said first dice lane,

wherein a plurality of said second transistors are circumscribed by a second dice lane of at least 10 microns width, and there are no second conductive connections to said plurality of said second transistors that cross said second dice lane, and

wherein said second dice lane is overlaying and aligned to said first dice lane; and

at least one thermal conducting path from at least one of said second single crystal transistors to an external surface of said device; and

a third layer comprising third single crystal transistors.

3. An Integrated Circuit device, comprising:

a first layer comprising first single crystal transistors;

a second layer overlaying said first layer, said second layer comprising second single crystal transistors,

wherein said second layer thickness is less than one micron,

wherein a plurality of said first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to said plurality of said first transistors that cross said first dice lane,

wherein a plurality of said second transistors are circumscribed by a second dice lane of at least 10 microns width, and there are no second conductive connections to said plurality of said second transistors that cross said second dice lane, and

wherein said second dice lane is overlaying and aligned to said first dice lane; and

at least one thermal conducting path from at least one of said second single crystal transistors to an external surface of said device,

wherein said thermal conducting path has a thermal conductivity greater than 20 W/m-K.

4. An Integrated Circuit device, comprising:

a first layer comprising first single crystal transistors;

a second layer overlaying said first layer, said second layer comprising second single crystal transistors,

wherein said second layer thickness is less than one micron,

wherein a plurality of said first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to said plurality of said first transistors that cross said first dice lane,

wherein a plurality of said second transistors are circumscribed by a second dice lane of at least 10 microns width, and there are no second conductive connections to said plurality of said second transistors that cross said second dice lane, and

wherein said second dice lane is overlaying and aligned to said first dice lane; and

at least one thermal conducting path from at least one of said second single crystal transistors to an external surface of said device,

wherein said first single crystal transistors are aligned to said second single crystal transistors with less than 200nm alignment error.

5. A 3D semiconductor device, comprising:

a first layer comprising first single crystal transistors;

a second layer overlying said first single crystal transistors and comprising second single crystal transistors,

wherein said second layer thickness is less than one micron,

wherein a plurality of said first single crystal transistors is circumscribed by a first guard ring,

wherein a plurality of said second single crystal transistors is circumscribed by a second guard ring, and

wherein said second guard ring overlays and is aligned to said first guard ring; and

at least one thermal conducting path from at least one of said second single crystal transistors to an external surface of said device.

6. A 3D semiconductor device, comprising:

a first layer comprising first single crystal transistors;

a second layer overlying said first single crystal transistors and comprising second single crystal transistors,

wherein said second layer thickness is less than one micron,

wherein a plurality of said first single crystal transistors is circumscribed by a first guard ring,

wherein a plurality of said second single crystal transistors is circumscribed by a second guard ring, and

wherein said second guard ring overlays and is aligned to said first guard ring; and

at least one thermal conducting path from at least one of said second single crystal transistors to an external surface of said device,

wherein said thermal conducting path has a thermal conductivity greater than 20 W/m-K.

7. A 3D semiconductor device, comprising:

a first layer comprising first single crystal transistors;

a second layer overlying said first single crystal transistors and comprising second single crystal transistors,

wherein said second layer thickness is less than one micron,

wherein a plurality of said first single crystal transistors is circumscribed by a first guard ring,

wherein a plurality of said second single crystal transistors is circumscribed by a second guard ring, and

wherein said second guard ring overlays and is aligned to said first guard ring; and

at least one thermal conducting path from at least one of said second single crystal transistors to an external surface of said device,

wherein said first single crystal transistors are aligned to said second single crystal transistors with less than 200nm alignment error.

8. A 3D semiconductor device, comprising:

a first layer comprising first single crystal transistors;

a second layer overlying said first single crystal transistors and comprising second single crystal transistors,

wherein said second layer thickness is less than one micron,

wherein a plurality of said first single crystal transistors is circumscribed by a first guard ring,

wherein a plurality of said second single crystal transistors is circumscribed by a second guard ring, and

wherein said second guard ring overlays and is aligned to said first guard ring; and

at least one thermal conducting path from at least one of said second single crystal transistors to an external surface of said device,

wherein the majority of the transistors comprised in said second layer have a thermal conducting path to said external surface.

9. A 3D semiconductor device, comprising:

a first structure comprising first single crystal transistors;

a second structure overlying said first single crystal transistors and comprising second single crystal transistors,

wherein at least one of said second single crystal transistors is at least partially self-aligned to at least one of said first single crystal transistors; and

at least one thermal conducting path from at least one of said second single crystal transistors to an external surface of said device.

10. A 3D semiconductor device, comprising:

a first structure comprising first single crystal transistors;

a second structure overlying said first single crystal transistors and comprising second single crystal transistors,

wherein at least one of said second single crystal transistors is at least partially self-aligned to at least one of said first single crystal transistors; and

at least one thermal conducting path from at least one of said second single crystal transistors to an external surface of said device,

wherein a plurality of said first single crystal transistors is circumscribed by a first guard ring, and plurality of said second single crystal transistors is circumscribed by a second guard ring, and

wherein said second guard ring overlays and is aligned to said first guard ring.

11. A 3D semiconductor device, comprising:

a first structure comprising first single crystal transistors;

a second structure overlying said first single crystal transistors and comprising second single crystal transistors,

wherein at least one of said second single crystal transistors is at least partially self-aligned to at least one of said first single crystal transistors; and

at least one thermal conducting path from at least one of said second single crystal transistors to an external surface of said device; and

a third structure comprising third single crystal transistors, said a portion of said third single crystal transistors form a logic circuit.

12. A 3D semiconductor device, comprising:

a first structure comprising first single crystal transistors;

a second structure overlying said first single crystal transistors and comprising second single crystal transistors,

wherein at least one of said second single crystal transistors is at least partially self-aligned to at least one of said first single crystal transistors; and

at least one thermal conducting path from at least one of said second single crystal transistors to an external surface of said device,

wherein said thermal conducting path has a thermal conductivity greater than 20 W/m-K.