Methods and apparatus for dynamic instruction controlled reconfigurable register file with extended precision

  • US RE40,883 E1
  • Filed: 04/19/2004
  • Issued: 08/25/2009
  • Est. Priority Date: 07/09/1998
  • Status: Expired due to Term
First Claim
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1. A processing apparatus for performing a multiply accumulate operation comprising:

  • a reconfigurable register file including an odd register file portion and an even register file portion;

    a first multiplexer to select the odd register file portion or the even register file portion to provide a first value;

    a second multiplexer to select the odd register file portion or the even register file portion to provide a second value;

    a multiplier for performing a multiply operation on the first value and the second value to produce a third value; and

    an accumulator for accumulating the third value with a fourth value to produce a result value, wherein the fourth value comprises a concatenated even and odd pair of values read from the reconfigurable register file.

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