Methods and apparatus for dynamic instruction controlled reconfigurable register file with extended precision

• US RE40,883 E1
• Filed: 04/19/2004
• Issued: 08/25/2009
• Est. Priority Date: 07/09/1998
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Pechanek, Gerald George, Barry, Edwin Franklin
• Primary Examiner(s): Tsai; Henry W. H.
• Application Number:
  US10/827,697
• Time in Patent Office: 1,954 Days
• Field of Search: 712/210, 712/24, 712/229, 712/218, 711/173, 711/170, 711/129, 708/503, 708/620, 708/496
• US Class Current: 712/210
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30105 Register structure
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format

Abstract

A reconfigurable register file integrated in an instruction set architecture capable of extended precision operations, and also capable of parallel operation on lower precision data is described. A register file is composed of two separate files with each half containing half as many registers as the original. The halves are designated even or odd by virtue of the register addresses which they contain. Single width and double width operands are optimally supported without increasing the register file size and without increasing the number of register file ports. Separate extended registers are also employed to provide extended precision for operations such as multiply-accumulate operations.

Claims

1. A processing apparatus for performing a multiply accumulate operation comprising:

a reconfigurable register file including an odd register file portion and an even register file portion;

a first multiplexer to select the odd register file portion or the even register file portion to provide a first value;

a second multiplexer to select the odd register file portion or the even register file portion to provide a second value;

a multiplier for performing a multiply operation on the first value and the second value to produce a third value; and

an accumulator for accumulating the third value with a fourth value to produce a result value, wherein the fourth value comprises a concatenated even and odd pair of values read from the reconfigurable register file.

2. The processing apparatus of claim 1 wherein the accumulator is further for writing the result value to the reconfigurable register file.

3. The processing apparatus of claim 1 wherein the accumulator is further for writing the result value to the reconfigurable register file as an even and odd pair.

4. The processing apparatus of claim 1 wherein the first multiplexer allows for single width accesses to the odd register file portion or the even register file portion.

5. The processing apparatus of claim 4 wherein the second multiplexer allows for single width accesses to the odd register file portion or the even register file portion.

6. A processing apparatus for performing an extended precision multiply accumulate operation comprising:

a reconfigurable register file including an odd register file portion and an even register file portion;

a first multiplexer to select the odd register file portion or the second even register file portion to provide a first value;

a second multiplexer to select the odd register file portion or the second even register file portion to provide a second value;

an extended precision register containing an extended value;

a multiplier for performing a multiply operation on the first value and the second value to produce a third value;

and

an extended accumulator for accumulating the third value with the extended value concatenated with a fourth value to produce a result value, wherein the fourth value comprises an even and odd pair read from the reconfigurable register file.

7. The processing apparatus of claim 6 wherein the accumulator is further for writing a first portion of the result value to the reconfigurable register file and a second portion of the result value to the extended precision register.

8. The processing apparatus of claim 6 wherein the accumulator is further for writing a first portion of the result value to the reconfigurable register file as an even and odd pair, and writing a second portion of the result value to the extended precision register.

9. A processing method for a processing apparatus comprising a reconfigurable register file including an odd register file portion and an even register file portion comprising the steps of:

selecting the odd register file portion or the even register file portion to provide a first value;

selecting the odd register file portion or the even register file portion to provide a second value;

multiplying the first value and the second value to produce a third value;

reading a fourth and a fifth value from the reconfigurable register file;

concatenating the fourth value with the fifth value to produce a concatenated value;

accumulating the third value with the concatenated value to produce a final result value.

10. The method of claim 9 wherein the third value and the fourth value comprise an even and odd pair read from the reconfigurable register file.

11. The method of claim 9 further comprising the step of:

storing the final result value to the reconfigurable register file.

12. The method of claim 11 wherein the final result includes an odd portion stored in the odd register file portion and an even portion stored in the even file portion.

13. A processing method for a processing apparatus comprising a reconfigurable register file including an odd register file portion and an even register file portion comprising the steps of:

selecting the odd register file portion or the even register file portion to provide a first value;

selecting the odd register file portion or the even register file portion to provide a second value;

multiplying the first value and the second value to produce a third value;

reading a fourth and a fifth value from the reconfigurable register file;

concatenating an extended value, and the fourth value with the fifth value to produce a concatenated value; and

accumulating the third value with the concatenated value to produce a final result value.

14. The processing method of claim 13 further comprising the, before the step of concatenating, the step of:

reading the extended value from an extended precision register.

15. The method of claim 13 further comprising the step of:

storing a portion of the final result value to the reconfigurable register file.

16. The method of claim 13 further comprising the step of:

storing a portion of the final result value to an extended precision register.

17. An apparatus for performing an operation with extended precision, the apparatus comprising:

at least two extended precision registers containing an extended value;

a register file containing a plurality of registers, the register file having at least two read ports;

an execution unit reading a first and a second value through the at least two read ports and connecting said execution unit'"'"'s output to the at least two extended precision registers;

a multiplexer, in response to a portion of a field in an instruction, selecting one of the at least two extended precision registers to provide a third value to the execution unit, said field in the instruction specifying one of at the least two extended precision registers to be written by the execution unit when the execution unit executes the instruction utilizing the first value, second value, and third value as inputs thereby increasing the precision of the operation.

18. The apparatus of claim 17 wherein the at least two extended precision registers having a first and second precision register, wherein the instruction further controlling whether to write the output of the execution unit to either the first or second precision register.

19. The apparatus of claim 17 wherein the at least two extended precision registers are loadable and readable by an application program.

20. The apparatus of claim 17 wherein the selection of one of the at least two extended precision registers as additional input to the execution unit is determined by a bit carried in the instruction.

21. The apparatus of claim 17 further comprising combinational logic receiving a bit from the instruction as input to determine whether to write output from the execution unit to the at least two extended precision registers.

22. The apparatus of claim 17 wherein the execution unit reads single width data types when reading the at least two read ports.

23. The apparatus of claim 17 wherein the execution unit reads double width data types when reading the at least two read ports.